Generally, in semiconductor device fabrication, well implantation is carried out after completion of shallow trench isolation (STI), STI filling, and STI planarization. FIGS. 1A to 1F are cross-sectional diagrams for explaining a known method of forming a well in a semiconductor device. Referring to FIG. 1A, a pad oxide layer 11 is grown on a silicon substrate 10 by thermal oxidation. A pad nitride (SiN) layer 12 and a pad tetraethylortho silicate (TEOS) layer 13 are sequentially deposited on the pad oxide layer 11.
Photoresist is coated on the pad TEOS layer 13. Exposing and developing are carried out on the photoresist layer to form a photoresist pattern 14 exposing a prescribed surface of the pad TEOS layer 13 corresponding to an STI area for semiconductor device isolation. The pad TEOS, nitride, and oxide layers 13, 12, and 11 are etched to expose a portion of the semiconductor substrate 10 using the photoresist pattern 14 as an etch mask. The exposed portion of the semiconductor substrate 10 is etched to form a trench 15.
Referring to FIG. 1B, after the photoresist pattern has been removed, an additional etch is carried out for STI rounding and divot depth adjustment. Further, referring to FIG. 1C, an oxide layer 16 is formed on an inside of the trench 15. Referring to FIG. 1D, a dielectric layer 17 is formed on the pad TEOS layer 13 to fill up the trench 15.
Referring to FIG. 1E, planarization including chemical mechanical polishing (CMP) is carried out on the dielectric layer 17 until the pad nitride layer 12 is exposed. As shown in FIG. 1F, the pad nitride layer is removed to expose the pad oxide layer 11 so that the dielectric layer 17 remains to fill up the trench only. Hence, an STI layer 17 is completed.
Referring to FIG. 1G, a photoresist pattern 18-1 exposing an n-well area is formed over the substrate 10. An n-well ion implantation is carried out on the substrate to form an n-well 19-1 in an active area of the substrate 10.
Referring to FIG. 1H, a photoresist pattern 18-2 exposing a p-well area is formed over the substrate 10. A p-well ion implantation is carried out on the substrate to form a p-well 19-2 in another active area of the substrate 10. Hence, final profiles of the n-well 19-1 and p-well 19-2 are completed.
However, according to the known method, a profile for a peak point of a dopant implanted by the well ion implantation is changed as shown in FIG. 1I. Namely, the dopant penetrating the STI layer 17 is unable to form a deep dopant profile. Additionally, the well peak point failing to be formed deep under the STI layer works as a leakage point to increase the current leakage between the bulk and junction, whereby semiconductor device performance is degraded.